Delay element circuit, voltage controlled oscillation circuit, and voltage controlled delay line circuit

遅延素子回路、電圧制御発振回路、および電圧制御遅延線回路

Abstract

【課題】電源電圧の変動の影響を受けにくい遅延素子回路を提供する。 【解決手段】本発明の遅延素子回路20Aは、ほぼ一定の電流を流すための電位を与えるバイアス信号を入力とするpチャネルMOSトランジスタ21と、ほぼ一定の電流を流すための電位を与えるバイアス信号を入力とするnチャネルMOSトランジスタ22と、pチャネルMOSトランジスタ21を介して電源に接続され、nチャネルMOSトランジスタ22を介して接地されており、入力信号のレベルを反転するインバータ回路23と、pチャネルMOSトランジスタ21とインバータ回路23との相互接続ノードと、nチャネルMOSトランジスタ22とインバータ回路23との相互接続ノードとに接続された抵抗素子24とを含んでなる。 【選択図】  図1
<P>PROBLEM TO BE SOLVED: To provide a delay element circuit that cannot be easily affected by a variation in a supply voltage. <P>SOLUTION: The delay element circuit 20A comprises a p-channel MOS transistor 21 that uses a bias signal for giving potential for allowing nearly a constant current to flow as input; an n-channel MOS transistor 22 that uses a bias signal for giving potential for allowing nearly a constant current to flow as input; an inverter circuit 23 that is connected to a power supply via the p-channel MOS transistor 21, is grounded via the n-channel MOS transistor 22, and inverts the level of an input signal; the interconnection node between the p-channel MOS transistor 21 and the inverter circuit 23; and a resistive element 24 that is connected to the interconnection node between the n-channel MOS transistor 22 and the inverter circuit 23. <P>COPYRIGHT: (C)2004,JPO

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    KR-100684067-B1February 16, 2007삼성전자주식회사주파수 범위 제한기능 및 온도보상 효과를 갖는 전압제어발진기